some verilog (engineering parody song)

To the tune of "drivers license" by Olivia Rodrigo:

I learned some Verilog last week Just like Manoj would think is hip 'Cause you were so excited for me To write the code that builds a chip So I wrote assign's among always Blocks bounded by end and begin

And you'll probably use that clock line To make the flip-flops fit The whole state changes at once No transients from a mistimed bit Yeah, I wrote assign's among always 'Cause why would I ever set gates by hand?

And I know sums are minimised with rectangles on Karnaugh's map-box And I just can't imagine rippling carries down so far, in real CMOS Guess you didn't mean to write code lower than around C 'Cause you said computing but I alone know the chip's beat

And Stephen Williams' tired Of handling changing rules but I kinda feel happy for him 'Cause he and contributors made a great tool Yeah, I wrote assign's among always And pictured I made CPUs anew

And I know sums are minimised with rectangles on Karnaugh's map-box Oh, and I just can't imagine rippling carries down so far, in real CMOS I guess you didn't mean to write code lower than around C 'Cause you said computing but I alone know the chip's beat

AND gates Bits' fates Magnitudes and signs In the full-adds Scratchpads Organised by timing ALU Passed thru 'Cause I know how to use pipelines

Flip-flops On-off Greater/equal/less In the flag bits We're caching On wafer's excess God, it's so slow Vivado But I know how to use pipelines

I know sums are minimised with rectangles on Karnaugh's map-box And I just can't imagine rippling carries down so far, in real CMOS Guess you didn't mean to write code lower than around C 'Cause you said computing but I alone know the chip's beat Yeah, you said computing but I alone know the chip's beat